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The hardware may accept or decline the change of state request, depending on the system status for example, overvoltage status, undervoltage status, and current measurements alter the system status.

A subsequent read from the Status register verifies if the design accepts the change of state. The drive system monitor latches status signals from the system so the signals are available as status register bits and direct outputs.

For example, the direct outputs can drive status LEDs. The pulse-width modulation PWM block triggers ADC conversion with a reset signal that resets the filters and control logic.

The design calculates:. When the settling time satisfies and the ADC conversion completes, the design sends an interrupt to the processor.

Additional noise in the system affects the performance value. By choosing to synchronize sampling to the quiet periods of the PWM waveform, signal quality is acceptable when sampled at 16 kHz despite the theoretical output data rate of The design has two separate filter paths: a control loop filter path and an overcurrent detection filter path.

The control loop filters have an offset correction feature for zero-offset correction. The filter output is a signed 16 bit 2's complement format.

A software configurable overcurrent output provides a direct output to disable the motor when under hardware control. The control loop and overcurrent detection filters use the same control bit for decimation selection.

The possible selections are:. The design performs synchronization between the ADC clock and the FPGA system clock at the output stage before the design delivers output data in the Avalon-MM interface slave registers.

You must apply appropriate timing constraints in the Quartus Prime software project to guarantee correct sampling of the ADC interface data.

Base the sampling on the clock to output specification of the ADC. To change the thresholds: edit the component settings in Qsys, regenerate the Qsys project, and recompile in the Quartus Prime software.

Each Avalon-ST interface can indicate eight under- or over-threshold violations corresponding to the eight channels of each of the two ADC modules that make up the dual ADC.

The design selectively enables latched errors for output to one or more drive system monitor modules via the under and over conduits.

The drive system monitors use the error signals to safely shut down the DC-DC converter and one or more drive axes in the event of an error condition such as overcurrent or overvoltage.

You can selectively set the error latches, to simulate error conditions, for test purposes. The DC-DC converter provides the boost function to increase the voltage.

It also provides a buck function during periods of regenerative braking to deliver power from the DC bus back to the low voltage source i.

The gate driving signals for the two phases are degrees out of phase so that they alternate in supplying current during buck-boost function, which gives smoother output current and voltage.

The control consists of two independent inner current loops and an outer voltage loop that regulates the DC bus voltage to a predetermined value e.

You can instantiate the Qsys component in a Qsys system and connected to the Nios II processor and other modules.

The register slave allows software access to the DC-DC converter parameters, control, and status. The conduits connect to various system-wide control and status signals that are outside the software domain.

The Qsys wrapper implements safety features, that you may use with external logic, to protect the system in the case of a malfunction.

The design gates the following two independent enable sources that enable the DC-DC converter. To operate correctly, the DC-DC converter requires regular feedback samples of the DC link voltage and the currents in the two switching phases inductor currents that you write through the Avalon-MM slave interface.

The sample timeout watchdog shuts down the DC-DC converter if it does not receive a new sample within a programmable timeout period.

The Convert DSP block sets the data format. This model uses signed-fractional data format for the feedback signals and the control math inside the DC-DC Control block.

In the PWM block, the design generates a triangular wave bounded within [ The design compares the triangular signal with current control signals bounded within [ You can extend the dead time by increasing the number of sample delays.

The enable bit remains cleared, and writing to the control register cannot set it again until the system negates the fault input.

The design supports FOC sensor control where the motor position feeds back to form a closed loop with position and speed PI control.

The design may sense the motor position by absolute resolver, EnDat, BiSS or incremental quadrature encoders.

The design supports FOC sensorless control in which the design samples and uses both the motor phase voltages and currents as the feedback to the control loop.

The DC bus voltage may drop during quick acceleration or rise during regeneration. If you do not expect the bus voltage to change much e.

The design integrates the speed estimator with the sliding mode observer SMO to allow a second order observer to calculate both estimated angle and estimated speed together.

In FOC sensorless mode, the motor starts initially in open loop with a requested speed and switches to sensorless mode after a preset time to allow the SMO to settle.

The observer, based on the electrical model, estimates the rotating back-EMF vector. The rotor position determines the direction of the back-EMF, which enables estimation of position.

At constant speed, back-EMF components are sinusoidal in quadrature, as are error signals. Considering voltage V and current I in one motor phase with resistance Rs , inductance Ls.

Net applied voltage V is at the motor terminal, and the centre of the motor is at 0 V. Aparm is non-dimensional, represents the electrical system dynamics.

Aparm should be close to 1 if the sample time is much faster than the motor time constant. Aparm and Bparm are constant and are calculated once during initialization of the software.

The back-EMF estimate may be noisy so the observer filters it and converts it to position. The design provides two methods:.

AobsError is back-EMF in d direction. Substituting Bemf equations into SMO equation:. The angle tracking observer is a standard feedback control system that guides the output y to the input u.

In this case, u is the unknown rotor electrical angle, y is the estimate of it. AObsError is K u - y. The estimate y tends towards u , but is filtered by K and G s , which helps to reduce noise.

Alpha and beta are constant. The design calculates them once during initialization of the software. The design derives various SMO parameters from the motor parameters for each motor type, such as resistance and inductance.

Other SMO parameters, and default values, are:. Arctan method of angle calculation only. The final two stages of the SMO are a low-pass filter on each component of the estimated BEMF followed by an inverse tangent arctan observer.

The output of the inverse tangent is the estimated angle. This parameter sets the sliding mode gain on the current observer.

This observer is responsible for estimating the BEMF signals that it ultimately feeds into the angle tracking observer. To adjust this parameter, run the motor and view the estimated angle waveform.

If it looks like an undistorted triangle no adjustment should be necessary. If the triangle looks distorted, while running at constant speed, adjust this parameter to clean it up.

The software reconstructs the motor current from the individual phase current readings using the Hall encoder state to determine which phase current is relevant.

FOC controls a motor's sinusoidal 3-phase currents in real time to create a smoothly rotating magnetic flux pattern, where the frequency of rotation corresponds to the frequency of the sine waves.

FOC controls the current vector to keep:. The reference design includes fixed-point and floating-point models that implement the FOC algorithm.

Each model calls a corresponding. The folding factor is set to a large value to minimize resource usage. Closed-loop simulation models validate that the FOC correctly controls a motor in simulation:.

The handshaking logic ensures synchronization between the software and hardware. The software sets up any changes to hardware parameters such as PI gains, writes new feedback currents, position feedback and torque command input data before starting the DSP Builder for Intel FPGAs calculation.

The DSP Builder for Intel FPGAs folding feature reuses physical resources such as multipliers and adders for different calculations with the VHDL generation automatically handling the complexity of building the time division multiplexed TDM hardware for the particular sample to clock rate ratio.

Intel compared floating- and fixed-point versions of the FOC algorithm with and without folding. In addition, Intel compared using a bit bit mantissa instead of standard single-precision bit bit mantissa floating point implementation.

Dual estimation, rather than joint estimation, with only one Kalman filter reduces the state matrix dimensions and may improve the estimation robustness.

The measurement equation is the same for both filters. In the above equations:. Download PDF. AN You can adapt the reference design or other motor types.

The development kit can take power from from a standard power supply or from a rechargeable battery pack, which shows the bidirectional power flow and battery state-of-charge estimation features.

Figure 1. Supported Motor Control Boards Table 1. AC and Servo Drive Systems AC and servo drive system designs comprise multiple distinct but interdependent functions to realize requirements to meet the performance and efficiency demands of modern motor control systems.

A typical drive system includes: Flexible pulse-width modulation PWM circuitry to switch the power stage transistors appropriately Motor control loops for single- or multiaxis control Industrial networking interfaces Position encoder interfaces Current, voltage, and temperature measurement feedback elements.

Monitoring functions, for example, for vibration suppression. Battery Management System Reference Design. You must charge the rechargeable battery to the level set by the specified charger before using it with the the Drive-on-Chip Reference Design.

Figure 2. XT60 Connector. Figure 3. HXT 4 mm Connector. Figure 4. Connecting Battery Charger. Table 2. Figure 5. The Quartus Prime software expands the archive and sets up the project, which may take some time.

FalconEye website. Figure 6. DIP SW2 is on the lower side of the board. Related tasks Applying Power to the Power Board. Download and install the reference design.

On Windows, building the project for the first time might take up to one hour to build the newlib C libraries with support for the Nios II floating point custom instructions.

Related tasks Downloading and Installing the Reference Design. Set up the motor control board with your development board. Note: Always remove power from the motor control power board, before reprogramming the FPGA, or removing power from the development boards.

Configure the FPGA with the reference design hardware. Never connect the battery and the power supply simultaneously.

Apply power to the motor control power board. The motor connected to axis 0 begins turning after a few seconds. The Nios II console shows further diagnostic messages as the control loop starts.

Related tasks Preparing the Rechargeable Battery. Check that the console display shows the correct FPGA and power board combination.

Close the window to reattach it to the System Console window. The tabs are grouped into two panes. Use the upper pane, starting with the Data Source tab to configure the reference design.

Use the lower pane, starting with the General tab to start demonstrations and monitor the state of the reference design.

Figure 7. Trace Setup Tab. Figure 8. Current Control Tab. Figure 9. Speed Control Tab. Figure Position Control Tab. Tuning the PI Controller Gains.

Monitoring Performance. Controlling the Speed and Position Demonstrations. General Tab. Waveform Demo Tab In the Demo drop-down menu select speed, position, or other demonstration.

Note: Large step changes in speed e. Waveform Demo Tab. Waveform Tab The Waveform tab shows the motor control waveform captured as a result of the trigger settings in the Trace Setup tab.

Waveform Tab. Battery Monitor The Battery Monitor tab shows the battery initial parameters, battery monitor control, and status of battery, including SOC and parameter values.

Battery Monitor Tab. You can tune the gain of each PI control loop. Kp proportional gain. Ki integral gain. The design applies the output voltage limit in two places to limit the applied voltage: Current PI loop integrator.

The scaling is the same as for the trigger function values. Enter values for Kp proportional gain and Ki integral gain.

Click Update Parameters. Enter values for Position Kp and Position Ki. The Drive-On-Chip Reference Design speed and position demonstrations show constant or varying speed and position.

If you select a non-constant waveform, the speed and position vary around this nominal value. Level trigger signal must match this value Rising Edge trigger signal must transition from below to above this value Falling Edge trigger signal must transition from above to below this value Either Edge triggers on both falling and rising edge conditions.

System Console can store up to 4, samples. Select a lower number of samples to make System Console update rate faster, and zoom in on the graph as the graph scale autosizes to the number of samples.

The MAX 10 ADC thresholds detect over or under voltage and current faults by comparing the sampled signals against preset limits. You must ensure each channel is converted at least once in the sequence.

Note: Failure to include all channels in the conversion sequence could cause damage to the Tandem Motion Power 48 V Board by, e.

Click OK. Compile the software application. Optionally configure the software application. Related reference Software Application Configuration Files.

You can modify the operation of the software application for the Drive-On-Chip Reference Design by editing some C source code and header files.

Table 3. Table 4. Configuration Macros. Undefined Normal operation. The array length must match the number of axes available e.

The resolver interface on the Tandem Motion-Power 48 V board converts the resolver outout into quadrature equivalent or Hall equivalent encoder signals.

The reference design supports a maximum of two axes so the third and fourth elements of the motors[] array are set to NULL for clarity.

The quartus. Mode: 1-bit Passive Serial. It uses 16 channels, channels 1 to 8 on each of the ADC submodules.

Table 5. Table 6. ADC Scaling. The scaling depends on the way the power board processes the signals e.

Signal Scaling Architecture. This figure shows a simplified block diagram of the scaling in the software application supporting the Tandem Motion-Power 48 V Board.

The FalconEye power board uses a simplified architecture with fewer feedback quantities and only sigma-delta ADCs available. Scaling of Motor Phase Current Samples The design treats motor phase current samples as dimensionless numbers in the FOC algorithm, rather than real current measurements.

Table 7. The scaling is also shown with a power-of-2 divisor to simplify integer arithmetic. Table 9. The table shows the required scale factors tthat the design calculates.

Calculation of Zero Offsets Offsets error arise in the ADC conversion process from a number of factors, including Component tolerance in sense circuits Offsets in sense amplifiers Errors in Vdd supply to sense amplifiers and ADCs Offsets in the ADC converters Offsets are most noticeable when converting low level signals where they lead to a larger error in percentage terms.

For the most crucial feedback, the design attempts to calculate and correct for the offsets.

Motor Phase Current Zero Offset The design calculates the zero offset for the motor phase current during startup.

The reference design applies scale factors to signals in the system console toolkit for diagnostic display in human readable, physical units e.

Table Scale Factors in System Console. Main Program. IRQ Routine. Qsys System for a Drive Axis. The Drive-On-Chip Reference Design six-channel PWM interface operates as three pairs of outputs, with each pair operating differentially to drive the upper and lower power transistors e.

PWM Counter Value. Configurable Timing Output Strobes. The reference design uses an evaluation version of the EnDat IP core version 2.

The reference design configures the EnDat IP core to respond to the trigger output that the PWM generates and reads a new position value.

Related information Mazet. The Drive-On-Chip Reference Design DC-link monitor uses an instance of the sinc3 filter module, similar to the instance that the sigma-delta interface uses, to monitor the DC-link voltage.

Offset Adjustment for DC-Link Monitor The design adds offset values to demodulator results to represent the bipolar input signal and to allow for zero-offset adjustment.

The Drive-On-Chip Reference Design drive system monitor is an interlock between the state of the system and the requested operation.

Drive System Monitor States State Name System State 0 Idle Reset state, moves immediately to preinit 1 Precharge PWM counter running, low side outputs enabled, voltage errors monitored 2 Prerun PWM counter running, low side outputs enabled, voltage and current errors monitored 3 Run PWM counter running, low and high side outputs enabled, voltage and current errors monitored 4 Error Error state, PWM counter running, outputs disabled 5 init PWM counter running, outputs disabled, voltage errors monitored 6 preinit PWM counter running, outputs disabled.

The resulting output is a count value representing the position of the motor shaft. A decimating sinc 3 filter in the FPGA then low-pass filters the serial input.

The sinc 3 filter does not require hardware multipliers. Sinc 3 Filter Figure Sinc 3 Filter Topology. The input samples pass through three integrator stages before a factor M decimates them.

The design reserves every Mth sample and discards M-1 samples. The design passes the reserved samples through three differentiators to produce a final output value.

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